Pipelining

Definition

• Increasing Throughout by overlapping executions of instructions
• At every pipeline stage, a new instruction is fed into the pipeline

Five Stages of Classic Pipeline

1. IF (Instruction Fetch): Getting instruction from instruction memory
2. ID (Instruction Decode): Determine instruction type
3. EX (Execute): ALU does computation
4. MEM (Memory): Read and write data memory
5. WB (Write Back): Write into register file

Pipeline Hazards

• Structural Hazards
  • Conflict over hardware structure
  • Instructions want to use the same hardware structure in the same clock cycle
• Data Hazards
  • Data dependence between instructions in pipeline
  • (EX)
    add r3,__,__
add __,r3,__ (r3 is used in two subsequent instructions)
• Branch Hazards/Control Hazards
  • Because branch takes time to know direction of branch
  • (EX)
    beq __,__,label
add __,__,__ (it is unknown is the add is going to happen or not until the branch equality is evaluated)