Hardware-Based Speculation

Motivation

With branch prediction, instructions after branches get fetched early into processor

  • So far, branch prediction lets us fetch insturctions after a branch, but we cannot execute them

If we execute instructions after a branch, what happens if the prediction is incorrect?

lw $r2, 0($r4)
beq $r2, $r3, target
add __,__,__
add __,__,__
; 100 more instructions that do not use $r2
target: add $r5, $r2, $r4
  • Branch Prediction: saving cycles because you can fetch before knowing the outcome
  • Speculation (speculative execution): Saving cycles because you can execute before knowing branch outcome

Storing Speculative Values#

  • For this to work, you need a place to store speculative values
  • Reorder Buffer
    • In order (like a queue)
    • Four fields
      • Instruction type
      • Destination Register
      • Value field
      • Read field (is instruction complete?)

Four Stages with Speculation#

  1. Issue: Send an instruction to a reservation station
  2. Execute: If operands are ready, then execute
  3. Write Result: Write to common data bus and the result is stored in the reorder buffer
  4. Commit: Write result from the reorder buffer into the register file
    1. On a branch mispredict, clear out instructions after a branch
LOOP:Issue1ExecuteMemoryWriteCommit1LD R2, 0 (R1)122345DADDIUR2,R2, #115671In orderSD R2, 0 (R1)232372Compute AddressDADDIUR1, R1, #42354,583Stores write to memory on commitBNE R2, R3, LOOP8734Single COB (1 CDB write per cycle)LD R2, 0 (R1)4657895This value is 6 because of a dependenceDADDIU R2,R2, #1491011NotesAssumptions1 integer ALU1 address computation unit1 branch unit (branches issue alone)2 insturctions can issue per cycle2 insturctions can commit per cycle
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